| 1. | Leak current detection accuracy test for each additional leak current setting
测试同一仪器每一额外泄漏电流定位之漏电侦察准确度 |
| 2. | Clients may be required to provide appropriate loading resistors for the leak current test
客户或须提供适当负载的电阻器作漏电测试之用。 |
| 3. | Value ) . the calibration will normally include measurement of output voltages and test for leak current detection accuracy
校正工作包括测量输出电压量及测试漏电侦察的准确度。 |
| 4. | Leak current detection accuracy test for the same equipment ( normally for not more than 7 leak current settings )
为同一仪器进行漏电侦察准确度测试。 (通常不会超过七个泄漏电流定位) |
| 5. | This article also study the principle with harmony wave analytic approaches monitoring the resistive weight of moa leak current and realize this requisition on hardwares circuit
本文还研究了用谐波分析法监测moa泄漏电流阻性分量的原理和实现这一方法对硬件电路的要求。 |
| 6. | Through the analysis of theoretic and testing data , it indicate this method can have been accurate to reflect the total resistive leak current and the resistive leak current of base wave
通过理论和实测数据分析表明，该方法能准确反映总阻性泄漏电流和阻性基波泄漏电流。 |
| 7. | Soi , namely silicon on insulator , device and ic have many advantages : low leak current , weak parasitic capacitance , low power loss , radiation hardness , and high integreted level
Soi ( silicononinsulator )器件及集成电路具有泄漏电流小、寄生电容小、功耗小、集成度高、抗辐射能力强等优点。 |
| 8. | Abstract : this paper introduces the principle of phase discrimination fo r leak c urrent protecting , and shows a leak current protecting system of phase discrimina tion based on 8031 single - chip computer
文摘:本文介绍了鉴相型漏电保护的原理，并提出了一种以8031单片计算机为核心的鉴相漏电保护装置。 |
| 9. | The machine contain main functions of four testing apparatus , it can automatic test leaking current , grounding electric resistance , dielectric intensity , resting voltage and print testing data
详细说明具备四种测试仪的全部主要技术性能，可连续自动测试漏电流、接地阻抗、电介质强度、剩余电压。可打印测试数据。 |
| 10. | Low power design of the hardware is divided into two levels : device level and system level . in device level , low power design mainly focuses on decreasing load capacity and leaking current
硬件低功耗设计有两个层次:器件级的低层次设计主要关注减少负载电容和漏电流;系统级的高层次设计主要关注减少无用的逻辑和无用的电路活动。 |
